1/4 rev. a structure silicon monolithic integrated circuit name of product dc-ac inverter control ic type ? function ? 36v high voltage process ? 1ch control with full-bridge ? lamp current and voltage sense feed back control ? sequencing easily achieved with soft start control ? short circuit protection with timer latch ? under voltage lock out and over voltage protection ? mode-selectable the operating or stand-by mode by stand-by pin ? burst mode controlled by pwm and dc input absolute maximum ratings? parameter symbol limits unit supply voltage vcc 36 v bst pin bst 40 v sw pin sw 36 v bst-sw voltage difference bst-sw 15 v operating temperature range topr -40+85 storage temperature range tstg -55+150 maximum junction temperature tjmax +150 power dissipation pd 1024* mw * pd derate at 5.6mw/ for temperature above ta = 25 (when mount ed on a pcb 70.0mm70.0mm1.6mm) operating condition parameter symbol limits unit supply voltage vcc 9.030.0 v bst voltage bst 5.037.5 v bst-sw voltage difference bst-sw 5.014.0 v oscillation frequency fout 30110 khz bct oscillation frequency fbct 0.051.00 khz
2/4 rev. a electric characteristicsta=25vcc=24vstb=3.0v ( this product is not designed to be radiation-resistant. ) parameter symbol limits unit conditions min. typ. max. whole device operating current icc1 2.2 5.0 ma fout=60khz, fb=sw=gnd, bst=open stand-by current icc2 0 10 a stand by control stand-by voltage h vsth 2.0 vcc v system stand-by voltage l vstl -0.3 1.0 v system vcc uvlo block operating voltage (vcc) v_vccuvp 6.17 6.50 6.83 v hesteresis width (vcc uvlo) Sv_vccuvp 0.37 0.50 0.63 v operating voltage (uvlo) v_uvp 1.80 1.85 1.90 v hesteresis width(uvlo) Sv_uvp 0.15 0.20 0.25 v operating voltage (ovp) v_ovp 3.10 3.20 3.30 v hesteresis width(ovp) Sv_ovp 0.15 0.20 0.25 v reg block reg output voltage vreg 7.35 7.50 7.65 v vcc>8.5v reg source current ireg 20 ma osc block rt output voltage vrt 1.05 1.50 1.95 v srt on resistor value rsrt 100 200 soft start block soft start time tss 2.5 5.0 10.0 ms fout=60khz bosc block bosc max voltage vbcth 2.16 2.25 2.34 v fbct=0.3khz bosc min voltage vbctl 0.6 0.7 0.8 v fbct=0.3khz bosc frequency fbct 291 300 309 hz bct=10000pf feed back block is threshold voltage vis1 1.225 1.250 1.275 v vs threshold voltage vvs 1.215 1.250 1.285 v is source current 1 iis1 0.9 a duty=2.45v is source current 2 iis2 40 50 60 a duty=0v is=1.0v vs source current ivs 0.9 a is comp detect voltage viscomp 0.606 0.625 0.644 v output block ln output sink resistance rsinkln 1.5 3 6 ln output source resistance rsourceln 5 10 20 hn output sink resistance rsinkhn 1.5 3 6 vbst-vsw=7.0v hn output source resistance rsourcehn 5 10 20 vbst-vsw=7.0v max duty max duty 46.0 48.5 49.5 % fout=60khz off period toff 100 200 400 ns drive output frequency fout 57.9 60 62.1 khz rt=100k timer latch block cp timer latch detect voltage vcp 1.9 2.0 2.1 v cp timer latch charge current icp 0.85 1.0 1.15 a fail on resistor value rfail 125 250 comp block comp over voltage detect voltage vcomp 3.88 4.0 4.12 v hysteresis width comp Svcomp 0.15 0.20 0.25 v
3/4 rev. a package dimensions block diagr am pin description pin no. pin name function pin no. pin name function 1 pgnd power ground for fet drivers 13 fail error indication signal output ( normal : l, error : open) 2 ln2 nmos fet driver (ch. 2) 14 cp external capacitor between cp and gnd for timer latch 3 bst2 boot-strap input for hn2 output 15 fb error amplifier output 4 hn2 nmos fet driver (ch. 2) 16 is error amplifier input 2 5 sw2 lower rail voltage for hn2 output 17 vs error amplifier input 1 6 vcc power supply input with uvlo protection 18 comp input of over voltage detector 7 stb stand-by switch 19 vlo external under voltage lock out and over voltage protection 8 srt external resister from srt to rt for adjusting the start-up triangle oscilator 20 sw1 lower rail voltage for hn1 output 9 rt external resistor between rt and gnd for adjustment frequency of saw tooth wave 21 hn1 nmos fet driver (ch. 1) 10 gnd ground 22 bst1 boot-strap input for hn1 output 11 bct external capacitor between bct and gnd for adjusting the burst triangle oscillator 23 reg regulator output 12 duty control burst-dimming by pwm signal or dc 24 ln1 nmos fet driver (ch. 1) ssop-b24 (unit:mm) BD9244AFV lot no. device mark stb block systemon/off osc block bosc block vcc rt bct duty vlo stb is duty block reg block vlo ?? vcc reg f/b block pwm block logic block output block ct vs fb protect block gnd comp cp srt reg hn2 ln2 ss block ct_counter ct bst2 sw2 fail hn1 ln1 bst1 sw1 pgnd ct
4/4 rev. a note for use . when designing the external circuit, including adequate margins for variation between external devices and ic. use adequate margins for steady state and transient characteristics. . the circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. the standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. . mounting failures, such as misdirection or miscounts, may harm the device. . a strong electromagnetic field may cause the ic to malfunction. . the gnd pin should be the location within 0.3v compared with the pgnd pin. . if the voltage between vcc and i/o pins or gnd and i/o pins is in opposite from the normal potential difference, unusual current flow into pins may occur which can destroy the ic. to avoid such occurrence it is recommended to place protection diodes for prevention against backward current flow. . BD9244AFV incorporate a built-in thermal shutdown circuit (tsd circuit). the thermal shutdown circuit (tsd circuit) is designed only to shut the ic off to prevent runaway thermal operation. it is not designed to protect the ic or guarantee its operation of the thermal shutdown circuit is assumed. . absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. moreover, the exact failure mode caused by short or open is not defined. physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings . . about the external fet, the parasitic capacitor may cause the g ate voltage to change, when the drain voltage is switching. make sure to leave adequate margin for this ic variation. . by stb voltage, BD9244AFV are changed to 2 states. therefore, d o not input stb pin voltage betwe en one stat e and the other state (1.02.0v). . the pin connected a connector need to connect to the resistor for electrical surge destruction. this ic is a monolithic ic which (as shown is fig.4)has p + substrate and between the various pins. a p-n junction is formed from this p layer of each pin. for example, the relation between each potential is as follows, (when gnd > pinb and gnd > pina, the p-n junction operates as a parasitic diode.) (when pinb > gnd > pina, the p-n junction operates as a parasitic transistor.) parasitic diodes can occur inevitably in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin fig.4. simplified structure of a bipolar ic other adjacent components parasitic diode (pinb) parasitic (pina) parasitic diode resistance p substrate (pina) transistor (npn) parasitic diode p substrate (pinb)
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